FPGAs: The “G” doesn’t stand for “Green” – but it could
FPGAs could help the telecom industry reduce power consumption.
In the last couple of years, service providers have developed a greater awareness of how they can take better control of their energy use and energy costs. For every piece of cable equipment produced, there is an associated, additional cost to cool that equipment.
This is why low power operation has become a key differentiator and a top selling point among equipment vendors. Increasingly today, equipment vendors that can meet system performance but do so with lower power consumption than rivals give themselves a better shot at becoming a vendor of choice.
Some cable operators are even requesting equipment with this design requirement. Equipment vendors turn around to their silicon providers, asking for a clear power reduction roadmap for future designs. The semiconductor technology that equipment vendors are adopting to meet this low power requirement, as well as other design goals, are field-programmable gate arrays (FPGAs).
FPGAs allow equipment vendors to integrate several electronic components in their designs into a single integrated circuit (IC), cutting not only the bill of materials (BOM) costs for the number of discrete chips and components they have in their equipment, but also reducing the amount of heat that needs to be extracted from the design.
FPGAs have other advantages over other ICs, as well. Let’s take a closer look at FPGA technology and how it is helping equipment companies meet the requirements for next-generation equipment.
OEMs across the globe are increasingly opting for FPGAs instead of application-specific integrated circuits (ASICs) or application-specific standard products (ASSPs) in order to reduce the time to market. FPGAs offer flexibility and facilitate rapid prototyping. FPGAs also offer an advantage of testing and verifying a concept in hardware without passing through the long fabrication process. Engineers can then make changes and can run a number of iterations on an FPGA circuit within hours, rather than in weeks or months.
As design requirements often change over a period of time, the cost of implementing these incremental changes to FPGAs are almost negligible as compared to the large expense associated with other ICs, such as ASICs and ASSPs.
Addressing next-generation applications requires satisfying mandates for extreme bandwidth, smart vision, ubiquitous computing, embedded security, safety and more. By enabling all programmable electronics systems, the industry’s “programmable imperative” is addressed by reducing exploding design costs and dramatically increasing design flexibility. Integrating more application functions into ever-fewer chips enabled by system to IC design tools and IP, plus a broad portfolio of programmable technologies, will shape the future of electronic systems.
Moving to an FPGA-based design gives equipment vendors and cable operators a clear path to a lower power solution.
The leading FPGA vendors manufacture their devices in the latest silicon process technologies – with each generation consistently lower in power – with higher logic capacity, and including an increased number of logic cells and DSPs than the previous generation of devices.
Today’s FPGAs are implemented in a low-power 28nm silicon process technology that yields a 40 percent reduction in power while doubling the amount of logic resources from the prior-generation 40nm process technology.
This increased capacity and low power provides equipment designers the ability to encode, filter and modulate any number of QAM signals on a single device. Designs can now provide up to 160 QAM channels over a single RF connector.
Larger FPGAs can support multiple ports, with each port containing the full RF spectrum (160 channels). System designers can also include J.83 encoding, as well as a traffic manager in a single device.
Consolidating a design into a single device reduces overall board space, reduces board layout complexity, reduces BOM and, most importantly, yields a lower-power solution.
This also means that functions that were once performed outside of the traditional headend equipment can now be combined into a single piece of equipment. As an example, designers can now integrate the RF combiner and RF upconverter external to a cable modem termination system (CMTS) or edge QAM into a single chip. This is an important advantage in the wake of the most recently released Converged Cable Access Platform (CCAP) specification from CableLabs.
The CCAP specification looks to combine narrowcast and broadcast services (voice, video and data) into a single piece of equipment. In the past, data and voice services were handled with a CMTS with upstream and downstream ports connected to a media access controller (MAC) residing on a single line card.
A modular approach was introduced, whereby the downstream physical layer was separated from the MAC board. This new piece of equipment, the edge QAM, handled not only the data and voice traffic from the CMTS, but also video content from a VOD server.
FPGAs will play a major role in the overall CCAP architecture. It has been demonstrated that the J.83 encoder, digital upconverter and DPD filter IP cores can be combined onto a single 28nm FPGA.
Multiple RF ports can also be combined onto a single device. Estimates show that up to four RF ports can fit into a single device and support six ports in the not-too-distant future.
Designers can configure multiple ports with any number of narrowcast and broadcast channels. Designers can also consolidate logic resources by multiplexing broadcast channels among the multiple RF ports. The end result provides a lower-power, streamlined and more efficient architecture.
One of the key benefits of the CCAP specification is to achieve significant environmental efficiencies. Figures 2 and 3 demonstrate examples of the space and power savings achieved by deployment of the CCAP in a typical system.
Figure 2 depicts a typical installation in a headend consisting of the various digital services, including broadcast, SDV, VOD and HSI equipment, plus the corresponding combiner and lasers/receivers. Figure 3 depicts the analogous installation when considering the deployment of equivalent CCAP equipment in a medium-size chassis.
An added benefit that FPGAs have over ASSPs and ASICs is the ability to provide code upgrades.
In the last 15 years, the cable industry has gone through a tremendous amount of change. The DOCSIS specification has undergone numerous iterations, from 1.0, to 1.1 (QoS, security), to 2.0 (S-CDMA for the upstream) and 3.0 (channel bonding, IPv6).
Customer demand, along with competition from competing broadband technologies, has required greater performance. But cable operators cannot reuse existing equipment for each change in the specification. Equipment vendors and cable operators must wait for new silicon from the chip vendors. Reuse of existing hardware and software is not possible. No leverage from previous development is possible.
FPGAs solve this dilemma with just a new code upgrade. Cable operators can perform system test and verification with updated code. Systems can be reused that eliminate the problem of recycling outdated equipment. The inherent flexibility of FPGAs is a perfect fit for an industry with specifications that are constantly evolving.
Today’s architecture is hardcoded with a defined number of downstream and upstream channels. It is just not possible to add additional channels, which limits the number of channels the MAC can support. There is no flexibility in the existing design and no room for improvement or code upgrades. Equipment developers can only add a multiple of the existing architecture.
FPGA vendors now offer devices that have both processors and FPGA logic on a single chip. These devices allow designers to integrate both MAC functions and scheduling into their FPGA designs.
Traditionally, design teams have implemented the MAC function on a separate device, either as a combined upstream/downstream MAC or as two separate MACs (modular design).
Meanwhile, the scheduler solution has been a software program residing on another external processor connected to the MAC. By combining the scheduler and MAC hardware and software functionality onto a single device, power is greatly reduced, as well as board real estate. A combined hardware/software solution also allows code to run much more efficiently.
In the near future, FPGAs will begin to be produced at the new 20nm process node. System designers can then expect the number of processor cores and logic resources of FPGAs to increase while the power consumption of these devices decreases further. This will allow design teams to integrate more functionality – both hardware and software – into a single device.
With FPGA technology, the overall headend solution can become highly programmable. The programmability of the overall solution they’ve created will provide cable operators with flexibility that has not been offered in previous architectures.
Equipment vendors can provide solutions into multiple markets with only a code change. Having a fully programmable solution allows equipment vendors to provide any number of broadcast to narrowcast channel ratios.
The appropriate annex setting can be configured during initial power up or can be downloaded during the manufacturing process. The inclusion of high-speed transceivers will allow a 10 Gbps Ethernet connection to external routers and servers. Design teams can implement more efficient routing algorithms, thus allowing lower latency on incoming packets.
Moving to an FPGA architecture certainly provides a clear roadmap to providing a lower power solution. The additional benefits of flexibility and programmability provide a competitive advantage to the equipment vendors over today's existing architectures. Ultimately, the cable operators will benefit by having a lower-power, fully flexible solution that can be reused when specifications are modified.
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